1. Field of the Invention
The present invention relates to a cache memory apparatus provided between a CPU (central processing unit) and a main memory in order to realize a high speed access, and more specifically to such a cache memory having a plurality of accessible ports.
2. Description of Related Art
In computer systems, a cache memory has been conventionally used as a means for speeding up access to a main memory. The cache memory system is based on a localization in space and in time in program access and data access operations. Once certain data in the main memory is accessed, the data is reserved in a cache memory which can be accessed at a speed higher than that of accessing the main memory, so that at a second and succeeding accesses to the same data, access is made to the cache memory, not the main memory, so that a required access time is shortened.
In a high speed system having a plurality of CPUs (central processing units), the most general method is to provide one cache memory to each of the CPUs. In this case, however, a complicated protocol has been necessary to ensure coincidence between the main memory and the respective cache memories, and therefore, the amount of hardware has been inevitably increased.
Therefore, a relatively small number of CPU systems have been constructed so that the cache memory is configured to be of a multi-port type, and a plurality of CPUs are coupled in common to the single cache memory. In this case, since the plurality of CPUs access to the common cache memory at random, a plurality of accesses often conflict with each other. Therefore, the accesses are allowed one by one in the order of accesses or in the order of priorities assigned to the CPUs.
For example, as shown in FIG. 1, first and second CPUs 1, 2 are coupled through a single 2-port cache memory apparatus 3 and a system bus 4 to a main memory 5. The cache memory includes a 2-port cache memory 6, a first controller 7 for controlling the 2-port cache memory on the basis of an access from the first CPU, and a controller 8 for controlling the 2-port cache memory on the basis of an access from the second CPU.
In this cache memory apparatus, since the cache memory is of the 2-port type, the first and second controllers can operate independently of each other unless access conflict occurs in a line to be accessed.
However, the above mentioned conventional cache memory has been disadvantageous in the following points:
For example, when a certain cache access (called an access "A") has become a miss and replacement will be performed, if another access (called an access "B") simultaneously occurs to access the same data, the access B will become missing, since the replacement for the access "A" has not yet been completed and therefore since the cache has not yet been updated. Therefore, replacement for the access "B" will be performed. However, since the data newly located in the cache by the replacement for the access "B" is the same as the data located by the replacement for the access "A", the data newly located in the cache by the replacement for the access "B" is redundant.
In addition, when the access "A" for a line is hit (i.e., is found or is acceptable) but before the access history information (LRU, FIFO, etc) corresponding to the hit line is updated, if the access B is made to the same line and is missed (i.e., not found or unacceptable), there is a possibility that the same block as that selected by the access "A" is replaced. In this case, the data hit in the access "A" is overwritten.
Furthermore, when both of the accesses A and B which access the same line but which designate different regions within the main memory are missed (i.e., not found), if replacement is performed before the access history information of the line in question is a updated, there will be possibility that the same block is selected and that data will be overwritten in the same block.